memory bandwidth中文是什么意思

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中文翻譯
造句

存儲(chǔ)帶寬

memory n. 1.記憶；記憶力；【自動(dòng)化】存儲(chǔ)器；信息存儲(chǔ)方式； ...
bandwidth of parallel memory 并行存儲(chǔ)帶寬
memory bus bandwidth 內(nèi)存總線帶寬
memory system bandwidth 存儲(chǔ)器系統(tǒng)的帶寬
bandwidth (帶寬)：電纜，鏈路或系統(tǒng)傳輸數(shù)據(jù)的能力。; 帶寬，通訊頻帶; 頻帶寬，誤差，范圍; 頻帶寬度; 頻寬；帶寬; 頻率帶寬度; 通帶寬度
if bandwidth 中頻帶寬
in memory of 紀(jì)念, 追念; 紀(jì)念，作為…的紀(jì)念; 以紀(jì)念...，為了紀(jì)念..; 以紀(jì)念……
in-memory 追憶
memory n. 1.記憶；記憶力；【自動(dòng)化】存儲(chǔ)器；信息存儲(chǔ)方式；存儲(chǔ)量。 2.回憶。 3.紀(jì)念。 4.死后的名聲，遺芳。 5.追想得起的年限[范圍]。 artificial memory 記憶法。 retentive memory 良好的記憶力。 a translation memory (電子計(jì)算機(jī)的)譯碼存儲(chǔ)器。 Keep your memory active. 好好記住，不要忘記。 It is but a memory. 那不過(guò)是往事而已。 bear [have, keep] in memory 記著，沒(méi)有忘記。 beyond [within] the memory of man [men] 在有史以前[以來(lái)]。 cherish the memory of (sb.) 懷念(某人)。 come to one's memory 想起，憶及，蘇醒。 commit to memory 記住。 from memory 憑記憶。 have a good [bad, poor, short] memory 記性好[壞]。 have no memory of 完全忘記。 If my memory serves me. 如果我的記性不錯(cuò)。 in memory of 紀(jì)念…。 of blessed [famous, happy, glorious] memory 故〔加在已死王公名上的頌詞〕 (King Charles of blessed memory 已故查理王)。 slip sb.'s memory 被某人一時(shí)忘記。 to the best of one's memory 就記憶所及。 to the memory of 獻(xiàn)給…〔著者書(shū)前紀(jì)念性題詞〕。 within living memory 現(xiàn)在還被人記著。
memory ( 開(kāi)啟除錯(cuò)
no memory 無(wú)存儲(chǔ)器
of memory 記憶
on memory of 為紀(jì)念……
absolute bandwidth 絕對(duì)帶寬
acquisition bandwidth 捕獲帶寬
actual bandwidth 實(shí)際帶寬
amplifer bandwidth 放大器帶寬
amplifier bandwidth 放大器帶寬
antenna bandwidth 天線帶寬
audio bandwidth 聲頻帶寬
available bandwidth 可用帶寬
b bandwidth 頻帶寬度
bandwidth allocation 帶寬分配
bandwidth amplifier 頻帶放大器
bandwidth characteristic 帶寬特性

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例句與用法

Memory bandwidth is very small
要求內(nèi)存帶寬較小。
This is the fastest way of animating , but its memory bandwidth is too high
它確實(shí)是一個(gè)完成動(dòng)畫(huà)的快速方法，但其對(duì)內(nèi)存帶寬要求過(guò)高。
3 thoroughly reviewed memory bandwidth requirement of sma processor and difference of various instruction fetch policies . to improve cache performance under sma model , the paper introduces hardware software co - operative optimization
3針對(duì)多線程模式下訪存負(fù)荷加重的問(wèn)題，為sma模型設(shè)計(jì)了軟硬件協(xié)同預(yù)取機(jī)制，并為sma模型設(shè)計(jì)了cachefilter來(lái)消減無(wú)效預(yù)取。
And to improve the efficient of the packet switching , researchers suggest people use the parallel packet switches ( pps ) , and pps has been studied as a way to overcome the memory bandwidth limitation and to scale - up switch speeds
在網(wǎng)絡(luò)速度要求不斷提高的情況下,存儲(chǔ)器件速度跟不上需求,許多的研究者提出嘗試使用多平面的交換結(jié)構(gòu)提高數(shù)據(jù)交換的速度,解決高速網(wǎng)絡(luò)中的交換問(wèn)題。
And it has significance in multimedia communication , digital multimedia broadcast and portable consumer electronics etc . the real - time implementation of video coding requires very high computation power and memory bandwidth
它面向移動(dòng)多媒體應(yīng)用,對(duì)新一代移動(dòng)多媒體通信、數(shù)字多媒體廣播、便攜式視聽(tīng)消費(fèi)電子產(chǎn)品等產(chǎn)業(yè)的發(fā)展具有重要意義。數(shù)字視頻數(shù)據(jù)壓縮的實(shí)時(shí)實(shí)現(xiàn)對(duì)處理器的計(jì)算能力和帶寬要求很高。
This is not only because the increased computing power also allows users to produce more and more complex datasets , but also because memory bandwidth grows at a significantly slower rate than processing power and becomes the major bottleneck when dealing with massive datasets
這不僅是因?yàn)橛?jì)算能力的增長(zhǎng)允許用戶來(lái)創(chuàng)建更為復(fù)雜的數(shù)據(jù)集，也是因?yàn)閮?nèi)存帶寬的發(fā)展速度明顯的低于處理器增長(zhǎng)的速度，而這成為處理大規(guī)模數(shù)據(jù)集的主要瓶頸。
In the part 2 of advanced audio video coding standard avs - p2 , many efficient coding tools are adopted in motion compensation , such as new motion vector prediction , symmetric matching , quarter precision interpolation , etc . however , these new features enormously increase the computational complexity and the memory bandwidth requirement , which make motion compensation a difficult component in the implementation of the avs hdtv decoder
在avs - p2中傳統(tǒng)的運(yùn)動(dòng)補(bǔ)償技術(shù)被進(jìn)一步改進(jìn)以獲得更好的編碼性能。這些新的特性包括：預(yù)測(cè)塊大小可變化1616到88基于矢量三角形的新型mv預(yù)測(cè)多參考幀最多2幀或4場(chǎng)直接或?qū)ΨQ模式匹配不限制的mv和1 4精度像素插值等。
The efficiency of the controller can be 36 . 36 % or 72 . 73 % when data length is 1 or 2 . when the data length is 4 or above , the efficiency can be 100 % . the effect that on - chip cache has on memory bandwidth is analyzed , and an on - chip cache scheme that can reduce 50 % reference data read
通過(guò)多體交錯(cuò)式存取,本文設(shè)計(jì)的ddrsdram控制器在存取數(shù)據(jù)長(zhǎng)度為1或2個(gè)字時(shí),帶寬利用率分別為36 . 36 %和72 . 73 % ,存取數(shù)據(jù)長(zhǎng)度為4個(gè)字時(shí),帶寬利用率可達(dá)到100 % ,滿足了高清實(shí)時(shí)解碼的要求。

百科解釋

Memory bandwidth is the rate at which data can be read from or stored into a semiconductor memory by a processor. Memory bandwidth is usually expressed in units of bytes/second, though this can vary for systems with natural data sizes that are not a multiple of the commonly used 8-bit bytes.

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